Many electrical and computer applications and components have critical timing requirements that compel generation of periodic clock waveforms that are precisely synchronized with a reference clock waveform. A phase-locked loop ("PLL") is one type of circuit that is widely used to provide an output signal having a precisely controlled frequency that is synchronous with the frequency of a received or input signal. Wireless communication devices, frequency synthesizers, multipliers and dividers, single and multiple clock generators, and clock recovery circuits are but a few examples of the manifold implementations of PLLs.
Frequency synthesis is a particularly common technique used to generate a high frequency clock from a lower frequency reference clock. In microprocessors, for example, an on-chip PLL can multiply the frequency of a low frequency input (off-chip) clock, typically in the range of 1 to 4 MHz, to generate a high frequency output clock, typically in the range of 10 to over 200 MHz, that is precisely synchronized with the lower frequency external clock. Another common use of PLLs is recovery of digital data from serial data streams by locking a local clock signal onto the phase and frequency of the data transitions. The local clock signal is then used to clock a flip-flop or latch receiving input from the serial data stream.
FIG. 1 is a block diagram of a typical PLL 10. PLL 10 comprises phase/frequency detector 12, charge pump 14, loop filter 16, voltage-controlled oscillator ("VCO") 18 and frequency divider 20. PLL 10 receives a reference clock signal CLK.sub.REF having a frequency F.sub.REF and generates an output clock signal CLK.sub.OUT having a frequency F.sub.OUT that is synchronized with the reference clock signal in phase. The output clock frequency is typically an integer (N) multiple of the reference frequency; with the parameter N set by frequency divider 20. Hence, for each reference signal period, there are N output signal periods or cycles.
Phase/frequency signal detector 12 receives on its input terminals two clock signals CLK.sub.REF and CLK*.sub.OUT (CLK.sub.OUT, with its frequency F.sub.OUT divided down by frequency divider 20). In a conventional arrangement, detector 12 is a rising edge detector that compares the rising edges of the two clock signals. Based on this comparison, detector 12 generates one of three states. If the phases of the two signals are aligned, the loop is "locked". Neither the UP nor the DOWN signal is asserted and VCO 18 continues to oscillate at the same frequency. If CLK.sub.REF leads CLK*.sub.OUT, than VCO 18 is oscillating too slowly and detector 12 outputs an UP signal proportional to the phase difference between CLK.sub.REF and CLK*.sub.OUT. Conversely, if CLK.sub.REF lags CLK*.sub.OUT, than VCO 18 is oscillating too quickly and detector 12 outputs a DOWN signal proportional to the phase difference between CLK.sub.REF and CLK*.sub.OUT. The UP and DOWN signals typically take the form of pulses having a width or duration corresponding to the timing difference between the rising edges of the reference and output clock signals. They have a complementary relationship such that neither is asserted at the same time and, if one is asserted, the other is not asserted.
Charge pump 14 generates a current I.sub.CP that controls the oscillation frequency F.sub.OUT of VCO 18. I.sub.CP is dependent on the signal output by phase/frequency detector 12. If charge pump 14 receives an UP signal from detector 12, indicating that CLK.sub.REF leads CLK*.sub.OUT, I.sub.CP is increased. If charge pump 14 receives a DOWN signal from detector 12, indicating that CLK.sub.REF lags CLK*.sub.OUT, I.sub.CP is decreased. If neither an UP nor a DOWN signal is received, indicating that the clock signals are aligned, charge pump 14 does not adjust I.sub.CP.
Loop filter 16 is positioned between charge pump 14 and VCO 18. Application of the charge pump output current I.sub.CP to loop filter 16 develops a voltage V.sub.LF across filter 16. V.sub.LF is applied to VCO 18 to control the frequency F.sub.OUT of the output clock signal. Filter 16 also removes out-of-band, interfering signals before application of V.sub.LF to VCO 18. A common configuration for a loop filter in a PLL is a simple single-pole, low-pass filter that can be realized with a single resistor and capacitor.
Oscillator 18 generates an oscillating output signal CLK.sub.OUT having a frequency F.sub.OUT proportional to the voltage V.sub.LF applied to VCO 18. Conventional voltage-controlled oscillators typically oscillate about a specific center frequency and have a relatively narrow frequency range or bandwidth. When CLK.sub.REF leads CLK*.sub.OUT, charge pump 14 increases I.sub.CP to develop a greater V.sub.LF across loop filter 16 which, in turn, causes VCO 18 to increase F.sub.OUT. Conversely, when CLK.sub.REF lags CLK*.sub.OUT, charge pump 14 decreases I.sub.CP to develop a lesser V.sub.LF across loop filter 16 which, in turn, causes VCO 18 to decrease F.sub.OUT. When CLK.sub.REF and CLK*.sub.OUT are aligned, V.sub.LF is not adjusted, and F.sub.OUT is kept constant. In this state, PLL 10 is in a "locked" condition.
The output clock signal is also looped back through (in some applications) frequency divider 20. The resultant output CLK*.sub.OUT is provided to phase/frequency detector 12 to facilitate the phase-locked loop operation. Frequency divider 20 divides F.sub.OUT by the multiplication factor N to obtain a divided clock. Divider 20 may be implemented using counters, shift registers, or through other methods familiar to those of ordinary skill in the art. Thus, PLL 10 compares the reference clock phase to the divided clock phase and eliminates any detected phase difference between the two by adjusting the frequency of the output clock.
A conventional charge pump circuit 50, suitable for implementation in PLL 10, is illustrated in schematic detail in FIG. 2. Charge pump 50 includes a "pump-up" p-channel CMOS ("PMOS") current mirror 54 and an associated "UP" PMOS switching transistor M5 coupled at an output node 51 to a "pump-down" n-channel CMOS ("NMOS") current mirror 56 and an associated "DOWN" NMOS switching transistor M6.
Current mirror 54 includes a mirror transistor M1 having a gate coupled to the gate of an associated mirror transistor M3. The sources of transistors M1 and M3 are coupled to a voltage supply V.sub.DD. The drain of transistor M1 is coupled to its gate, in order to insure that the transistor remains in saturation, and the drain of transistor M3 is coupled to the source of UP switching transistor M5. Current mirror 56 is implemented with NMOS mirror transistors M2 and M4. The gates of transistors M2 and M4 are coupled together, and their sources are tied to ground. The drain of transistor M2 is coupled to its gate, and the drain of transistor M4 is coupled to the source of DOWN switching transistor M6. The drains of switching transistors M5 and M6 are coupled to output node 51.
A reference current source providing a reference current I.sub.REF is disposed between the drains of mirror transistors M1 and M2. Based on the signals applied to the gates of switching transistors M5 and M6 by the phase/frequency detector (which would be connected to charge pump 50 as shown in FIG. 1), the reference current is mirrored through either pump-up current mirror 54 or through pump-down current mirror 56 to direct an output current I.sub.CP to or from output node 51. When an "UP" signal is applied to switching transistor M5, consisting of a voltage level sufficient to place transistor M5 in saturation and thereby turn it "on", the reference current is mirrored in the M3-M5 branch. Charge pump 50 thereby outputs a current I.sub.CP equal to +I.sub.REF. Conversely, if a "DOWN" signal is applied to switching transistor M6, transistor M6 turns on and the reference current is mirrored in the M6-M4 branch. Charge pump 50 outputs a current I.sub.CP equal to -I.sub.REF.
A loop filter 52 is coupled to output node 51. The charge pump current I.sub.CP is input to filter 52 to generate a voltage V.sub.LF that is applied to a voltage-controlled oscillator (which would be connected to loop filter 52 as shown in FIG. 1). Loop filter 52, as shown, consists of a series-connected resistor R and capacitor C1 in parallel with a capacitor C2. Filter 52 could take alternative forms, such as simply a series-connected resistor and capacitor. If I.sub.CP =+I.sub.REF, the integrating capacitor formed by the combination of capacitors C1 and C2 is charged and V.sub.LF increases. If I.sub.CP =-I.sub.REF, the integrating capacitor is discharged and V.sub.LF decreases. The oscillating frequency is thereby adjusted as necessary to correct phase differences detected by the phase/frequency detector.
In typical charge pumps such as pump 50, the UP and DOWN pulses generated by the phase/frequency detector must have a minimum width (duration) in order to ensure that the charge pump has time to turn on. Small phase differences that would result in generation by the detector of UP and DOWN pulses having a duration less than this minimum width are referred to as being in the "dead zone" of the circuit. The dead zone, then, is essentially a range of phase differences in response to which the phase detector cannot produce pulses of sufficient duration to activate the charge pump. When in the dead zone, the oscillator may drift from the center frequency since the charge pump is unable to correct phase differences occurring within this zone. Accordingly, frequency synthesizers exhibit poor frequency selectivity while in the dead zone. From the standpoint of avoiding dead zone problems, then, it is desirable to increase the duration or "turn on" time of the ON/OFF pulses produced by the phase/frequency detector.
During the charge pump switching time, spikes or "spurs" may result on the output node from sources such as switching noise and transistor mismatch in the current mirrors. This is detrimental to the performance of the PLL or frequency synthesizer and, when implemented in RF transceivers, ultimately degrades the sound quality and clarity (selectivity). From the standpoint of noise and spur reduction, then, it is desirable to decrease the charge pump switching time and the duration of the detector ON/OFF pulses.
Hence, there exists a trade-off between designing for better spur and noise performance through decreasing charge pump switching time and detector pulse duration, and designing for a smaller dead zone by increasing the detector pulse duration. The minimum pulse duration for dead zone removal is dictated by the switching time performance of the charge pump. Previous approaches for improving frequency selectivity, such as inclusion of an active loop filter, lead to excessive current consumption levels not suitable for commercial applications.
In view of the above, there is a need for a charge pump that overcomes the problems of the prior art.